1. Field of the Invention
The present invention relates to a method for the channel-synchronous switching of the signalling information within configurable digital multi-plexers to which a number of incoming and outgoing PCM-links are connected with a frame structure of M time slots each of P bits which time slots have to be re-arranged wherein for each of said links there is used at least one time slot for the transmission of a synchronizing signal or of a notification word and at least one time slot for the transmission of the signalling information of the intelligence channels occupying the remaining time slots wherein in each signalling time slot of a frame there is transmitted the signalling information of two intelligence channels and wherein with the aid of an ancillary equipment at the input side the contents of the signalling time slots of a superframe are lined-up to a signalling bit stream and are split-up at the output side onto the time slots used for signalling. The invention relates further to a circuit arrangement for carrying out said method.
2. Description of the Prior Art
In digital trunk networks there is set the task to re-arrange at nodal exchanges arbitraryly the individual channels or time slots of the connected PCM-links in accordance with a desired network configuration, wherein said configuration remains fixed during a shorter or longer period of time and the PCM-links of one local destination can by combined to a higher order multi-plex.
The following description relates exclusively to PCM-links which are provided for each direction of transmission with a separate path each with 32 channels of 64 kbit/s, corresponding to a bit rate of 2.times.2048 kbit/s. 30 channels of said 32 channels are used for the transmission of speech bytes, one channel (time slot No. 0) is reserved for synchronization purposes and the transmission of a notification word and one channel (time slot No. 16) is used as signalling channel.
To those skilled in the art it is obvious that the following description may be applied also to multiplexes with another, especially higher number of channels. This is true as long as the re-arrangement can be executed at the time slot level, i.e. that only one intelligence channel is provided per time slot and that during each signalling time slot of a frame the signalling information of two intelligence channels is transmitted.
The re-arrangement of individual time slots leads to a re-arrangement of the time slots within the multiplexes of the individual PCM-links. To each of said time slots there belongs a signalling information which is separately transmitted for the channels of one PCM-link over its time slots No. 16 according to CCITT protocol No. 7.
The through-switching and new formation of the multiplexes is performed by so-called intelligent primary multiplexers being able to arbitrarily exchange the individual 64 kbit/s channels of several incoming and outgoing 2.048 Mbit/s signals, in the following called 2 Mbit/s signals. There are used mainly commercially available integrated circuits as through-switching elements which elements are able to re-arrange complete bytes. Said bytes are identical with the data words of the time slots of the 2 Mbit/s frame structure according to CEPT standards.
By an ancillary equipment the incoming 2 Mbit/s signal is usually subdivided into two new bit streams which have again the CEPT frame structure with 32 time slots of 8 bits each. One of said bit streams is identical in its structure with the incoming 2 Mbit/s signal where a distinctive time slot is allocated to each 64 kbit/s channel. The other bit stream contains within one frame the lining-up of all time slots No. 16 of one CEPT superframe and thus the signalling information of all 30 intelligence channels, each with 64 kbit/s.
But each byte corresponding to a time slot of the above second named bit stream contains the signalling information of two channels. Therefore it is not possible to have re-arranged these signalling bytes by the through-switching element in the same manner than the speech bytes.
A known solution of the above problem is usually inherently given by the through-switching element by the provision of a processor conform interface allowing the access to each individual incoming and outgoing bit. With the aid of said interface it is possible to read out the signalling information as 8 bit words, to store them in a buffer store and to re-insert the signalling information as a newly arranged 4 bit word into the correct half time slot of the outgoing bit stream.
This solution results in a heavy load of the processor which load increases with increasing frequency of change of the signalling information of the incoming channels. Depending on the working capacity of the processor this may lead to a distortion of the signalling information with simultaneous changes of condition of several signalling words.
To lower said processor load there was already used a solution (Newbridge) wherein with the aid of additional hardware changes of condition of signalling words are detected so that the processor was discharged from the continuous comparison between old and new signalling information and had to be active only when signalling bits have to be changed and/or when due to a new configuration of the network the re-arranging addresses have to be changed.